Threshold voltage setting method for layer selection by multi-level operation in channel stacked NAND flash memor

Do Bin Kim; Dae Woong Kwon; Wandong Kim; Byung Gook Park

doi:10.1166/jnn.2017.14043

Threshold voltage setting method for layer selection by multi-level operation in channel stacked NAND flash memor

Do Bin Kim, Dae Woong Kwon, Wandong Kim, Byung Gook Park

Seoul National University

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we propose a modified channel-stacked array with a layer selection by multi-level operation (LSM) and a new string select transistors (SSTs) threshold voltage (V_th) setting method that all the SSTs on each layer are set to target V_th by using boosted body operation. To verify the validity of the new method in LSM, TCAD simulations are performed. It is verified that the V_th values of SSTs are set to the target V_th values by the new method. Moreover, memory operations are examined in TCAD simulation by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

Original language	English
Pages (from-to)	3386-3389
Number of pages	4
Journal	Journal of Nanoscience and Nanotechnology
Volume	17
Issue number	5
DOIs	https://doi.org/10.1166/jnn.2017.14043
State	Published - 2017

Bibliographical note

Publisher Copyright:
© Copyright 2017 American Scientific Publishers.

Keywords

3D Stacked NAND Flash Memory, Layer Selection by Multi-Level Operation (LSM).

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10.1166/jnn.2017.14043

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title = "Threshold voltage setting method for layer selection by multi-level operation in channel stacked NAND flash memor",

abstract = "In this paper, we propose a modified channel-stacked array with a layer selection by multi-level operation (LSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to target Vth by using boosted body operation. To verify the validity of the new method in LSM, TCAD simulations are performed. It is verified that the Vth values of SSTs are set to the target Vth values by the new method. Moreover, memory operations are examined in TCAD simulation by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.",

keywords = "3D Stacked NAND Flash Memory, Layer Selection by Multi-Level Operation (LSM).",

author = "Kim, \{Do Bin\} and Kwon, \{Dae Woong\} and Wandong Kim and Park, \{Byung Gook\}",

year = "2017",

doi = "10.1166/jnn.2017.14043",

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pages = "3386--3389",

journal = "Journal of Nanoscience and Nanotechnology",

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T1 - Threshold voltage setting method for layer selection by multi-level operation in channel stacked NAND flash memor

AU - Kim, Do Bin

AU - Kwon, Dae Woong

AU - Kim, Wandong

AU - Park, Byung Gook

PY - 2017

Y1 - 2017

N2 - In this paper, we propose a modified channel-stacked array with a layer selection by multi-level operation (LSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to target Vth by using boosted body operation. To verify the validity of the new method in LSM, TCAD simulations are performed. It is verified that the Vth values of SSTs are set to the target Vth values by the new method. Moreover, memory operations are examined in TCAD simulation by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

AB - In this paper, we propose a modified channel-stacked array with a layer selection by multi-level operation (LSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to target Vth by using boosted body operation. To verify the validity of the new method in LSM, TCAD simulations are performed. It is verified that the Vth values of SSTs are set to the target Vth values by the new method. Moreover, memory operations are examined in TCAD simulation by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

KW - 3D Stacked NAND Flash Memory, Layer Selection by Multi-Level Operation (LSM).

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M3 - Article

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SN - 1533-4880

VL - 17

SP - 3386

EP - 3389

JO - Journal of Nanoscience and Nanotechnology

JF - Journal of Nanoscience and Nanotechnology

IS - 5

ER -

Threshold voltage setting method for layer selection by multi-level operation in channel stacked NAND flash memor

Abstract

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