System-level verification of CDMA modem ASIC

In this paper, we present a system-level verification methodology which is used to verify the design of CDMA (Code Division Multiple Access) modem ASIC. To make the system-level verification feasible, the models for modulator of base station, fading channel and AGC loop were developed under the C environment. Behavioral modeling of a microcontroller was also carried out using VHDL to provide the ASIC with realistic input data, and the netlist of CDMA modem ASIC is loaded on to a hardware accelerator, which is interfaced with VHDL simulator. Finally, simulation was performed by executing an actual CDMA call processing software. This method was proved to be effective in both discovering in advance malfunctions of ASIC when embedded in the system and reducing simulation time by a factor of as much as 20 in the case of gate-level simulation. The designed ASIC which consists of 90,000 gates and 29K SRAMs is now successfully working in the real mobile-station on its first fab-out.