Shared CSD complex constant multiplier for parallel FFT processors

Tram Thi Bao Nguyen; Hanho Lee

doi:10.1109/ISOCC.2015.7401648

Shared CSD complex constant multiplier for parallel FFT processors

Tram Thi Bao Nguyen, Hanho Lee

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix -24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.

Original language	English
Title of host publication	ISOCC 2015 - International SoC Design Conference
Subtitle of host publication	SoC for Internet of Everything (IoE)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	27-28
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2015.7401648
State	Published - 8 Feb 2016
Event	12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2 Nov 2015 → 5 Nov 2015

Publication series

Name	ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Conference

Conference	12th International SoC Design Conference, ISOCC 2015
Country/Territory	Korea, Republic of
City	Gyeongju
Period	2/11/15 → 5/11/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

CSD
Fast Fourier transform (FFT)
complex constant multiplier
mixed radix

Access to Document

10.1109/ISOCC.2015.7401648

Cite this

Nguyen, T. T. B., & Lee, H. (2016). Shared CSD complex constant multiplier for parallel FFT processors. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) (pp. 27-28). Article 7401648 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2015.7401648

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title = "Shared CSD complex constant multiplier for parallel FFT processors",

abstract = "This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix -24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.",

keywords = "CSD, Fast Fourier transform (FFT), complex constant multiplier, mixed radix",

author = "Nguyen, {Tram Thi Bao} and Hanho Lee",

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Nguyen, TTB & Lee, H 2016, Shared CSD complex constant multiplier for parallel FFT processors. in ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)., 7401648, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), Institute of Electrical and Electronics Engineers Inc., pp. 27-28, 12th International SoC Design Conference, ISOCC 2015, Gyeongju, Korea, Republic of, 2/11/15. https://doi.org/10.1109/ISOCC.2015.7401648

Shared CSD complex constant multiplier for parallel FFT processors. / Nguyen, Tram Thi Bao; Lee, Hanho.
ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. p. 27-28 7401648 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix -24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.

AB - This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix -24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.

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KW - Fast Fourier transform (FFT)

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KW - mixed radix

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Nguyen TTB, Lee H. Shared CSD complex constant multiplier for parallel FFT processors. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc. 2016. p. 27-28. 7401648. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). doi: 10.1109/ISOCC.2015.7401648

Shared CSD complex constant multiplier for parallel FFT processors

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Bibliographical note

Keywords

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