Response speed of negative capacitance FinFETs

Daewoong Kwon; Yu Hung Liao; Yen Kai Lin; Juan Pablo Duarte; Korok Chatterjee; Ava J. Tan; Ajay K. Yadav; Chenming Hu; Zoran Krivokapic; Sayeef Salahuddin

doi:10.1109/VLSIT.2018.8510626

Response speed of negative capacitance FinFETs

Daewoong Kwon, Yu Hung Liao, Yen Kai Lin, Juan Pablo Duarte, Korok Chatterjee, Ava J. Tan, Ajay K. Yadav, Chenming Hu, Zoran Krivokapic, Sayeef Salahuddin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

38 Scopus citations

Abstract

We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested-per-stage delay as small as 7.2 ps.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	49-50
Number of pages	2
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510626
State	Published - 25 Oct 2018
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Conference

Conference	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

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10.1109/VLSIT.2018.8510626

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Kwon, D., Liao, Y. H., Lin, Y. K., Duarte, J. P., Chatterjee, K., Tan, A. J., Yadav, A. K., Hu, C., Krivokapic, Z., & Salahuddin, S. (2018). Response speed of negative capacitance FinFETs. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 49-50). Article 8510626 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510626

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title = "Response speed of negative capacitance FinFETs",

abstract = "We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested-per-stage delay as small as 7.2 ps.",

author = "Daewoong Kwon and Liao, \{Yu Hung\} and Lin, \{Yen Kai\} and Duarte, \{Juan Pablo\} and Korok Chatterjee and Tan, \{Ava J.\} and Yadav, \{Ajay K.\} and Chenming Hu and Zoran Krivokapic and Sayeef Salahuddin",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

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doi = "10.1109/VLSIT.2018.8510626",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Kwon, D, Liao, YH, Lin, YK, Duarte, JP, Chatterjee, K, Tan, AJ, Yadav, AK, Hu, C, Krivokapic, Z & Salahuddin, S 2018, Response speed of negative capacitance FinFETs. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510626, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 49-50, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510626

Response speed of negative capacitance FinFETs. / Kwon, Daewoong; Liao, Yu Hung; Lin, Yen Kai et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 49-50 8510626 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yadav, Ajay K.

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N2 - We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested-per-stage delay as small as 7.2 ps.

AB - We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested-per-stage delay as small as 7.2 ps.

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Response speed of negative capacitance FinFETs

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