Abstract
As the importance and complexity of System-on-Chip (SoC) testing increase, research to enhance test efficiency is being conducted. Among these, research is ongoing to reduce the number of pins used in testing through internal test modules in the Device Interface Board (DIB) application area. However, the existing test modules were designed without considering the actual mass production environment, making them unsuitable for application in the actual chip fabrication process. In this paper, we propose a method that offers enhanced error detection capabilities and high parallelism, implementing additional functionalities required for mass production, making it applicable to actual manufacturing processes.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - International SoC Design Conference 2024, ISOCC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 410-411 |
| Number of pages | 2 |
| ISBN (Electronic) | 9798350377088 |
| DOIs | |
| State | Published - 2024 |
| Event | 21st International System-on-Chip Design Conference, ISOCC 2024 - Sapporo, Japan Duration: 19 Aug 2024 → 22 Aug 2024 |
Publication series
| Name | Proceedings - International SoC Design Conference 2024, ISOCC 2024 |
|---|
Conference
| Conference | 21st International System-on-Chip Design Conference, ISOCC 2024 |
|---|---|
| Country/Territory | Japan |
| City | Sapporo |
| Period | 19/08/24 → 22/08/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- error detection
- functional test
- system on chip
- test efficiency