Parallel architecture for concatenated polar-CRC codes

Seunghun Oh; Hanho Lee

doi:10.1109/ISOCC.2017.8368846

Parallel architecture for concatenated polar-CRC codes

Seunghun Oh, Hanho Lee

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a parallel encoding and decoding method using concatenated polar-CRC codes to get high data throughput. Based on the proposed method, parallel architecture for concatenated polar-CRC codes is proposed. The proposed parallel concatenated polar-CRC decoding has better BER performance compared to conventional SC polar decoding without performance degradation in 3 dB SNR region.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	173-174
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368846
State	Published - 29 May 2018
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 5 Nov 2017 → 8 Nov 2017

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Conference

Conference	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	5/11/17 → 8/11/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

Architecture
CRC codes
Concatenated codes
Polar codes
Successive cancellation decoding

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10.1109/ISOCC.2017.8368846

Cite this

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title = "Parallel architecture for concatenated polar-CRC codes",

abstract = "This paper presents a parallel encoding and decoding method using concatenated polar-CRC codes to get high data throughput. Based on the proposed method, parallel architecture for concatenated polar-CRC codes is proposed. The proposed parallel concatenated polar-CRC decoding has better BER performance compared to conventional SC polar decoding without performance degradation in 3 dB SNR region.",

keywords = "Architecture, CRC codes, Concatenated codes, Polar codes, Successive cancellation decoding",

author = "Seunghun Oh and Hanho Lee",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

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doi = "10.1109/ISOCC.2017.8368846",

language = "English",

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Oh, S & Lee, H 2018, Parallel architecture for concatenated polar-CRC codes. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 173-174, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 5/11/17. https://doi.org/10.1109/ISOCC.2017.8368846

Parallel architecture for concatenated polar-CRC codes. / Oh, Seunghun; Lee, Hanho.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 173-174 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a parallel encoding and decoding method using concatenated polar-CRC codes to get high data throughput. Based on the proposed method, parallel architecture for concatenated polar-CRC codes is proposed. The proposed parallel concatenated polar-CRC decoding has better BER performance compared to conventional SC polar decoding without performance degradation in 3 dB SNR region.

KW - Architecture

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KW - Concatenated codes

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KW - Successive cancellation decoding

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BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

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Parallel architecture for concatenated polar-CRC codes

Abstract

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Keywords

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