Novel Boosting Scheme Using Asymmetric Pass Voltage for Reducing Program Disturbance in 3-Dimensional NAND Flash Memory

In this paper, novel boosting scheme using asymmetric pass voltage ( \text{V}-{\mathrm{ pass}} ) is proposed to obtain high channel boosting potential and to reduce program disturbance in 3-D NAND flash memory. The proposed scheme has the same program bias and timing conditions as conventional self-boosting except for \text{V}-{\mathrm{ pass}} voltages applied to both adjacent word-lines of selected word-line (WL_sel). Reduced \text{V}-{\mathrm{ pass}} ( \text{V}-{\mathrm{ pass1}} =\,\,\text{V}-{\mathrm{ pass}} - {\Delta }\text{V} ) is applied to previous word-line (WL -{\rm n-{1}} ) of WL_sel and increased \text{V}-{\mathrm{ pass}} ( \text{V}-{\mathrm{ pass2}} =\,\,\text{V}-{\mathrm{ pass}}+{\Delta }\text{V} ) is applied to next word-line (WL -{\rm n+{1}} ). In this scheme, the \text{V}-{\mathrm{ pass1}} cuts the channel off and causes local boosting when the channel potentials of inhibit strings are boosted up. Meanwhile, the \text{V}-{\mathrm{ pass2}} compensates the program speed reduction of selected cell (cell_sel) induced by the decreased voltage of the \text{V}-{\mathrm{ pass1}}. Through the measurements of program disturbance in fabricated devices, it is revealed that the program disturbance is significantly improved without the reduction of program speed by the proposed scheme. Furthermore, the \text{V}-{\mathrm{ pass1}} and \text{V}-{\mathrm{ pass2}} are optimized to maximize the improvement.