Low latency check node unit architecture for nonbinary LDPC decoding

Huyen Pham Thi; Hanho Lee

doi:10.1109/APCCAS.2016.7803986

Low latency check node unit architecture for nonbinary LDPC decoding

Huyen Pham Thi, Hanho Lee

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.

Original language	English
Title of host publication	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	400-401
Number of pages	2
ISBN (Electronic)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7803986
State	Published - 3 Jan 2017
Event	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 25 Oct 2016 → 28 Oct 2016

Publication series

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Conference

Conference	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/16 → 28/10/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

check-node unit
min-max
nonbinary LDPC

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10.1109/APCCAS.2016.7803986

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Thi, H. P., & Lee, H. (2017). Low latency check node unit architecture for nonbinary LDPC decoding. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 400-401). Article 7803986 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803986

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abstract = "This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.",

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year = "2017",

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doi = "10.1109/APCCAS.2016.7803986",

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Thi, HP & Lee, H 2017, Low latency check node unit architecture for nonbinary LDPC decoding. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803986, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 400-401, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 25/10/16. https://doi.org/10.1109/APCCAS.2016.7803986

Low latency check node unit architecture for nonbinary LDPC decoding. / Thi, Huyen Pham; Lee, Hanho.
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 400-401 7803986 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.

AB - This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.

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Low latency check node unit architecture for nonbinary LDPC decoding

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