Improvement of the tail component in retention time distribution using Buffered N- Implantation with Tilt and Rotation (BNITR) for 0.2 um DRAM cell and beyond

Ilgweon Kim; Namsung Kim; Hyuckchai Jung; Hoyup Kwon; Seunghan Ok; Jongmin Kim; Pilbo Sim; Jooseog Park; Daeyoung Park; Sungho Jang

Improvement of the tail component in retention time distribution using Buffered N- Implantation with Tilt and Rotation (BNITR) for 0.2 um DRAM cell and beyond

Ilgweon Kim, Namsung Kim, Hyuckchai Jung, Hoyup Kwon, Seunghan Ok, Jongmin Kim, Pilbo Sim, Jooseog Park, Daeyoung Park, Sungho Jang

Hyundai Micro Electronics Co, Ltd

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N- Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.

Original language	English
Pages (from-to)	86-87
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
State	Published - 2000
Externally published	Yes
Event	2000 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 13 Jun 2000 → 15 Jun 2000

Cite this

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title = "Improvement of the tail component in retention time distribution using Buffered N- Implantation with Tilt and Rotation (BNITR) for 0.2 um DRAM cell and beyond",

abstract = "The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N- Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.",

author = "Ilgweon Kim and Namsung Kim and Hyuckchai Jung and Hoyup Kwon and Seunghan Ok and Jongmin Kim and Pilbo Sim and Jooseog Park and Daeyoung Park and Sungho Jang",

year = "2000",

language = "English",

pages = "86--87",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 Symposium on VLSI Technology ; Conference date: 13-06-2000 Through 15-06-2000",

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Improvement of the tail component in retention time distribution using Buffered N- Implantation with Tilt and Rotation (BNITR) for 0.2 um DRAM cell and beyond. / Kim, Ilgweon; Kim, Namsung; Jung, Hyuckchai et al.
In: Digest of Technical Papers - Symposium on VLSI Technology, 2000, p. 86-87.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - Improvement of the tail component in retention time distribution using Buffered N- Implantation with Tilt and Rotation (BNITR) for 0.2 um DRAM cell and beyond

AU - Kim, Ilgweon

AU - Kim, Namsung

AU - Jung, Hyuckchai

AU - Kwon, Hoyup

AU - Ok, Seunghan

AU - Kim, Jongmin

AU - Sim, Pilbo

AU - Park, Jooseog

AU - Park, Daeyoung

AU - Jang, Sungho

PY - 2000

Y1 - 2000

N2 - The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N- Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.

AB - The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N- Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.

UR - http://www.scopus.com/inward/record.url?scp=0033719265&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0033719265

SN - 0743-1562

SP - 86

EP - 87

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2000 Symposium on VLSI Technology

Y2 - 13 June 2000 through 15 June 2000

ER -

Improvement of the tail component in retention time distribution using Buffered N- Implantation with Tilt and Rotation (BNITR) for 0.2 um DRAM cell and beyond

Abstract

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