High-speed Serial Interface using PWAM Signaling Scheme

Hwan Ung Kim; Jin Ku Kang

doi:10.1109/ISOCC56007.2022.10031330

High-speed Serial Interface using PWAM Signaling Scheme

Hwan Ung Kim, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a novel PWAM signaling scheme, which improves the high-speed data transmission capability by increasing the minimum pulse width compared to the conventional PWAM scheme. In addition, versus the existing PAM, the power efficiency of the transceiver employing a novel PWAM signaling scheme is improved by the PWM modulator based on CMOS logic. The 10-Gb/s transceiver designed for a 0.18-μm CMOS process consumes 229 mW and has a power efficiency of 22.9 pJ/bit.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	255-256
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031330
State	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 19 Oct 2022 → 22 Oct 2022

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	19/10/22 → 22/10/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

CMOS
low power
pulse amplitude modulation (PAM)
pulse width modulation (PWM)
serial link
transceiver

Access to Document

10.1109/ISOCC56007.2022.10031330

Cite this

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title = "High-speed Serial Interface using PWAM Signaling Scheme",

abstract = "This paper presents a novel PWAM signaling scheme, which improves the high-speed data transmission capability by increasing the minimum pulse width compared to the conventional PWAM scheme. In addition, versus the existing PAM, the power efficiency of the transceiver employing a novel PWAM signaling scheme is improved by the PWM modulator based on CMOS logic. The 10-Gb/s transceiver designed for a 0.18-μm CMOS process consumes 229 mW and has a power efficiency of 22.9 pJ/bit.",

keywords = "CMOS, low power, pulse amplitude modulation (PAM), pulse width modulation (PWM), serial link, transceiver",

author = "Kim, {Hwan Ung} and Kang, {Jin Ku}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

year = "2022",

doi = "10.1109/ISOCC56007.2022.10031330",

language = "English",

series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

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Kim, HU & Kang, JK 2022, High-speed Serial Interface using PWAM Signaling Scheme. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 255-256, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 19/10/22. https://doi.org/10.1109/ISOCC56007.2022.10031330

High-speed Serial Interface using PWAM Signaling Scheme. / Kim, Hwan Ung; Kang, Jin Ku.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 255-256 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a novel PWAM signaling scheme, which improves the high-speed data transmission capability by increasing the minimum pulse width compared to the conventional PWAM scheme. In addition, versus the existing PAM, the power efficiency of the transceiver employing a novel PWAM signaling scheme is improved by the PWM modulator based on CMOS logic. The 10-Gb/s transceiver designed for a 0.18-μm CMOS process consumes 229 mW and has a power efficiency of 22.9 pJ/bit.

AB - This paper presents a novel PWAM signaling scheme, which improves the high-speed data transmission capability by increasing the minimum pulse width compared to the conventional PWAM scheme. In addition, versus the existing PAM, the power efficiency of the transceiver employing a novel PWAM signaling scheme is improved by the PWM modulator based on CMOS logic. The 10-Gb/s transceiver designed for a 0.18-μm CMOS process consumes 229 mW and has a power efficiency of 22.9 pJ/bit.

KW - CMOS

KW - low power

KW - pulse amplitude modulation (PAM)

KW - pulse width modulation (PWM)

KW - serial link

KW - transceiver

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BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

Y2 - 19 October 2022 through 22 October 2022

ER -

High-speed Serial Interface using PWAM Signaling Scheme

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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