Abstract
In this paper, we present a novel modified algorithm and architecture to compute Elliptic Curve Cryptographic point multiplication. The proposed algorithm significantly reduces the number of point addition operations. Furthermore, the field multiplication operations are scheduled to perform simultaneously to reduce the latency. As a result, our algorithm and architecture reduce the hardware complexity compared to others, while the required time for point multiplication is kept at a reasonable value. The simulation result on Xilinx Virtex-7 FPGA shows that the proposed architecture offers an improvement in hardware complexity up to 68% and much better efficiency compared to others.
Original language | English |
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Title of host publication | ISOCC 2015 - International SoC Design Conference |
Subtitle of host publication | SoC for Internet of Everything (IoE) |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 265-266 |
Number of pages | 2 |
ISBN (Electronic) | 9781467393089 |
DOIs | |
State | Published - 8 Feb 2016 |
Event | 12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2 Nov 2015 → 5 Nov 2015 |
Publication series
Name | ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) |
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Conference
Conference | 12th International SoC Design Conference, ISOCC 2015 |
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Country/Territory | Korea, Republic of |
City | Gyeongju |
Period | 2/11/15 → 5/11/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- architecture
- bit-serial
- elliptic curve cryptography
- point multiplication