High-speed 8B/10B encoder coding table

Yong Woo Kim, Beomseok Shin, Jin Ku Kang

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

This letter presents a high-speed 8B/10B encoder design using a simplified coding table. The proposed encoder also includes a modified disparity control block. Logic simulation and synthesis have been done for the performance verification. After synthesized with a CMOS 0.18 μm process, the proposed design shows the operating frequency of 343MHz with no latency. The synthesized chip area is 1886 μm2 with 189 logic gates. The proposed 8B/10B encoder shows the overall performance improvement compared to previous approaches.

Original languageEnglish
Pages (from-to)581-585
Number of pages5
JournalIEICE Electronics Express
Volume5
Issue number16
DOIs
StatePublished - 25 Aug 2008

Keywords

  • 8B/10B encoder
  • CMOS
  • Disparity
  • Simplified encoding table

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