High-performance RF-interconnect for 3D stacked memory

Ahmed Alzahmi; Nahid Mirzaie; Chung Ching Lin; Insoo Kim; Gyung Su Byun

doi:10.1109/ISOCC.2017.8368793

High-performance RF-interconnect for 3D stacked memory

Ahmed Alzahmi, Nahid Mirzaie, Chung Ching Lin, Insoo Kim, Gyung Su Byun

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	109-110
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368793
State	Published - 29 May 2018
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 5 Nov 2017 → 8 Nov 2017

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Conference

Conference	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	5/11/17 → 8/11/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

3D ICs
High bandwidth memory (HBM)
Optimization
RF Transceiver
Through-silicon-via (TSV)

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10.1109/ISOCC.2017.8368793

Cite this

Alzahmi, A., Mirzaie, N., Lin, C. C., Kim, I., & Byun, G. S. (2018). High-performance RF-interconnect for 3D stacked memory. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 109-110). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368793

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title = "High-performance RF-interconnect for 3D stacked memory",

abstract = "A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.",

keywords = "3D ICs, High bandwidth memory (HBM), Optimization, RF Transceiver, Through-silicon-via (TSV)",

author = "Ahmed Alzahmi and Nahid Mirzaie and Lin, {Chung Ching} and Insoo Kim and Byun, {Gyung Su}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

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doi = "10.1109/ISOCC.2017.8368793",

language = "English",

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Alzahmi, A, Mirzaie, N, Lin, CC, Kim, I & Byun, GS 2018, High-performance RF-interconnect for 3D stacked memory. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 109-110, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 5/11/17. https://doi.org/10.1109/ISOCC.2017.8368793

High-performance RF-interconnect for 3D stacked memory. / Alzahmi, Ahmed; Mirzaie, Nahid; Lin, Chung Ching et al.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 109-110 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - High-performance RF-interconnect for 3D stacked memory

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AU - Mirzaie, Nahid

AU - Lin, Chung Ching

AU - Kim, Insoo

AU - Byun, Gyung Su

PY - 2018/5/29

Y1 - 2018/5/29

N2 - A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.

AB - A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.

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T2 - 14th International SoC Design Conference, ISOCC 2017

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ER -

High-performance RF-interconnect for 3D stacked memory

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Keywords

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