High-efficient nonbinary LDPC decoder with early layer decoding schedule

Thang Xuan Pham; Hanho Lee

doi:10.1109/ISCAS51556.2021.9401072

High-efficient nonbinary LDPC decoder with early layer decoding schedule

Thang Xuan Pham, Hanho Lee

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Increasing nonbinary low density parity check (NB-LDPC) decoder throughput is challenging. This paper considers nonbinary quasi-cyclic LDPC code features to propose an early layered decoding schedule. The proposed method can eliminate idle time introduced by emptying pipeline stages after each layered decoding process, as well as increase decoder throughput. Layout results using TSMC 90-nm CMOS technology confirm that the proposed decoding schedule improved throughput with almost the same hardware complexity compared to the state-of-the-art NB-LDPC decoder. In particular, the proposed approach achieved considerably improved throughput and efficiency compared with predecessors when both early layer decoding schedule and early decoding termination were enabled.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401072
State	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE

Keywords

Decoder
Decoding schedule
Message reduction
Nonbinary low density parity-check
Quasi-cyclic codes

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10.1109/ISCAS51556.2021.9401072

Cite this

Pham, T. X., & Lee, H. (2021). High-efficient nonbinary LDPC decoder with early layer decoding schedule. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401072 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401072

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title = "High-efficient nonbinary LDPC decoder with early layer decoding schedule",

abstract = "Increasing nonbinary low density parity check (NB-LDPC) decoder throughput is challenging. This paper considers nonbinary quasi-cyclic LDPC code features to propose an early layered decoding schedule. The proposed method can eliminate idle time introduced by emptying pipeline stages after each layered decoding process, as well as increase decoder throughput. Layout results using TSMC 90-nm CMOS technology confirm that the proposed decoding schedule improved throughput with almost the same hardware complexity compared to the state-of-the-art NB-LDPC decoder. In particular, the proposed approach achieved considerably improved throughput and efficiency compared with predecessors when both early layer decoding schedule and early decoding termination were enabled.",

keywords = "Decoder, Decoding schedule, Message reduction, Nonbinary low density parity-check, Quasi-cyclic codes",

author = "Pham, {Thang Xuan} and Hanho Lee",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401072",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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Pham, TX & Lee, H 2021, High-efficient nonbinary LDPC decoder with early layer decoding schedule. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401072, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401072

High-efficient nonbinary LDPC decoder with early layer decoding schedule. / Pham, Thang Xuan; Lee, Hanho.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401072 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - High-efficient nonbinary LDPC decoder with early layer decoding schedule

AU - Pham, Thang Xuan

AU - Lee, Hanho

PY - 2021

Y1 - 2021

N2 - Increasing nonbinary low density parity check (NB-LDPC) decoder throughput is challenging. This paper considers nonbinary quasi-cyclic LDPC code features to propose an early layered decoding schedule. The proposed method can eliminate idle time introduced by emptying pipeline stages after each layered decoding process, as well as increase decoder throughput. Layout results using TSMC 90-nm CMOS technology confirm that the proposed decoding schedule improved throughput with almost the same hardware complexity compared to the state-of-the-art NB-LDPC decoder. In particular, the proposed approach achieved considerably improved throughput and efficiency compared with predecessors when both early layer decoding schedule and early decoding termination were enabled.

AB - Increasing nonbinary low density parity check (NB-LDPC) decoder throughput is challenging. This paper considers nonbinary quasi-cyclic LDPC code features to propose an early layered decoding schedule. The proposed method can eliminate idle time introduced by emptying pipeline stages after each layered decoding process, as well as increase decoder throughput. Layout results using TSMC 90-nm CMOS technology confirm that the proposed decoding schedule improved throughput with almost the same hardware complexity compared to the state-of-the-art NB-LDPC decoder. In particular, the proposed approach achieved considerably improved throughput and efficiency compared with predecessors when both early layer decoding schedule and early decoding termination were enabled.

KW - Decoder

KW - Decoding schedule

KW - Message reduction

KW - Nonbinary low density parity-check

KW - Quasi-cyclic codes

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M3 - Conference contribution

AN - SCOPUS:85109024028

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

Y2 - 22 May 2021 through 28 May 2021

ER -

High-efficient nonbinary LDPC decoder with early layer decoding schedule

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