Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction

Junsu Yu; Kyung Kyu Min; Yeonwoo Kim; Daewoong Kwon; Bvung Gook Park

doi:10.1109/SNW51795.2021.00016

Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction

Junsu Yu, Kyung Kyu Min, Yeonwoo Kim, Daewoong Kwon, Bvung Gook Park

Seoul National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

To investigate metal-ferroelectric-insulator-semiconductor (MFlS) stack design guidelines for its applications, the ferroelectricity in various IL thicknesses were investigated. As a result, IL has leaky insulator characteristics rather than an ideal dielectric and the MFlS stack shows a critical difference in ferroelectric characteristics.

Original language	English
Title of host publication	2021 Silicon Nanoelectronics Workshop, SNW 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487819
DOIs	https://doi.org/10.1109/SNW51795.2021.00016
State	Published - 2021
Event	26th Silicon Nanoelectronics Workshop, SNW 2021 - Virtual, Online, Japan Duration: 13 Jun 2021 → …

Publication series

Name	2021 Silicon Nanoelectronics Workshop, SNW 2021

Conference

Conference	26th Silicon Nanoelectronics Workshop, SNW 2021
Country/Territory	Japan
City	Virtual, Online
Period	13/06/21 → …

Bibliographical note

Publisher Copyright:
© 2021 IEEE. All rights reserved.

Access to Document

10.1109/SNW51795.2021.00016

Cite this

Yu, J., Min, K. K., Kim, Y., Kwon, D., & Park, B. G. (2021). Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction. In 2021 Silicon Nanoelectronics Workshop, SNW 2021 (2021 Silicon Nanoelectronics Workshop, SNW 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW51795.2021.00016

@inproceedings{a3ddb1f4e23b43e99088c8559e528309,

title = "Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction",

abstract = "To investigate metal-ferroelectric-insulator-semiconductor (MFlS) stack design guidelines for its applications, the ferroelectricity in various IL thicknesses were investigated. As a result, IL has leaky insulator characteristics rather than an ideal dielectric and the MFlS stack shows a critical difference in ferroelectric characteristics.",

author = "Junsu Yu and Min, {Kyung Kyu} and Yeonwoo Kim and Daewoong Kwon and Park, {Bvung Gook}",

year = "2021",

doi = "10.1109/SNW51795.2021.00016",

language = "English",

series = "2021 Silicon Nanoelectronics Workshop, SNW 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 Silicon Nanoelectronics Workshop, SNW 2021",

address = "United States",

}

Yu, J, Min, KK, Kim, Y, Kwon, D & Park, BG 2021, Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction. in 2021 Silicon Nanoelectronics Workshop, SNW 2021. 2021 Silicon Nanoelectronics Workshop, SNW 2021, Institute of Electrical and Electronics Engineers Inc., 26th Silicon Nanoelectronics Workshop, SNW 2021, Virtual, Online, Japan, 13/06/21. https://doi.org/10.1109/SNW51795.2021.00016

Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction. / Yu, Junsu; Min, Kyung Kyu; Kim, Yeonwoo et al.
2021 Silicon Nanoelectronics Workshop, SNW 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 Silicon Nanoelectronics Workshop, SNW 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction

AU - Yu, Junsu

AU - Min, Kyung Kyu

AU - Kim, Yeonwoo

AU - Kwon, Daewoong

AU - Park, Bvung Gook

PY - 2021

Y1 - 2021

N2 - To investigate metal-ferroelectric-insulator-semiconductor (MFlS) stack design guidelines for its applications, the ferroelectricity in various IL thicknesses were investigated. As a result, IL has leaky insulator characteristics rather than an ideal dielectric and the MFlS stack shows a critical difference in ferroelectric characteristics.

AB - To investigate metal-ferroelectric-insulator-semiconductor (MFlS) stack design guidelines for its applications, the ferroelectricity in various IL thicknesses were investigated. As a result, IL has leaky insulator characteristics rather than an ideal dielectric and the MFlS stack shows a critical difference in ferroelectric characteristics.

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U2 - 10.1109/SNW51795.2021.00016

DO - 10.1109/SNW51795.2021.00016

M3 - Conference contribution

AN - SCOPUS:85124885500

T3 - 2021 Silicon Nanoelectronics Workshop, SNW 2021

BT - 2021 Silicon Nanoelectronics Workshop, SNW 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th Silicon Nanoelectronics Workshop, SNW 2021

Y2 - 13 June 2021

ER -

Yu J, Min KK, Kim Y, Kwon D, Park BG. Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction. In 2021 Silicon Nanoelectronics Workshop, SNW 2021. Institute of Electrical and Electronics Engineers Inc. 2021. (2021 Silicon Nanoelectronics Workshop, SNW 2021). doi: 10.1109/SNW51795.2021.00016

Guideline of optimum interfacial layers in metal-ferroelectric-insulator-semiconductor structure for gate stack and ferroelectric tunnel junction

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