Gate stack technology for nanoscale devices

Byoung Hun Lee, Paul Kirsch, Seungchul Song, Rino Choi, Rajarao Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Si-based devices.

Original languageEnglish
Title of host publication2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Pages206-207
Number of pages2
DOIs
StatePublished - 2006
Externally publishedYes
Event2006 IEEE Nanotechnology Materials and Devices Conference, NMDC - Gyeongju, Korea, Republic of
Duration: 22 Oct 200625 Oct 2006

Publication series

Name2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Volume1

Conference

Conference2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Country/TerritoryKorea, Republic of
CityGyeongju
Period22/10/0625/10/06

Keywords

  • Gate stack
  • High transport channel
  • High-k dielectrics

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