Electrical characteristics of metal-oxide-semiconductor capacitor with high-κ/metal gate using oxygen scavenging process

It has been widely accepted that the mismatch of lattice constants between HfO₂ and Si generates interface traps at the HfO₂-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO₂ film (<2 nm) has been inserted as an interlayer (IL) between HfO₂ and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO₂/IL SiO₂ stack as a scavenging layer to absorb oxygens in the SiO₂ and various annealing conditions were applied to optimize the thickness of the SiO₂. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS).