Abstract
A 15 GHz power amplifier design for 5G applications is presented in this paper. The proposed power amplifier consists in a three-stage architecture. A low complex pre-distortion circuit is designed as the first stage. Since the CMOS process suffers from poor intrinsic gain (gm∗ro), especially in the millimeter wave band, the Darlington pair driver stage is exploited to maximize the power gain. A FET-stack structure is used to enable high voltage operation and thus increase the output power. The proposed power amplifier is designed and simulated in a standard 130nm CMOS process. The simulation results show that the proposed power amplifier can attain 1dB compression point (P1dB) of 18.9 dBm with a power added efficiency (PAE) of 26% under 3.6 V and 1.8 V dual voltage supply.
Original language | English |
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Title of host publication | 2018 IEEE International Conference on Electro/Information Technology, EIT 2018 |
Publisher | IEEE Computer Society |
Pages | 808-811 |
Number of pages | 4 |
ISBN (Electronic) | 9781538653982 |
DOIs | |
State | Published - 18 Oct 2018 |
Event | 2018 IEEE International Conference on Electro/Information Technology, EIT 2018 - Rochester, United States Duration: 3 May 2018 → 5 May 2018 |
Publication series
Name | IEEE International Conference on Electro Information Technology |
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Volume | 2018-May |
ISSN (Print) | 2154-0357 |
ISSN (Electronic) | 2154-0373 |
Conference
Conference | 2018 IEEE International Conference on Electro/Information Technology, EIT 2018 |
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Country/Territory | United States |
City | Rochester |
Period | 3/05/18 → 5/05/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Keywords
- 5G communication
- CMOS
- Darlington pair
- Ku band
- Millimeter wave
- Power amplifier
- Pre-distortion technique