Counter-based Eye-open Monitoring System Design for High-speed Serial Interface

Kyung Sub Son; Namyong Kim; Jin Ku Kang

doi:10.1109/ISOCC47750.2019.9078519

Counter-based Eye-open Monitoring System Design for High-speed Serial Interface

Kyung Sub Son, Namyong Kim, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Abstract-An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. Through the estimated eye-opening information, the eye calculates the open area and the optimal sampling point. The size and phase of the sampling point are controlled by 5-bit, respectively. The proposed eye-open monitor was fabricated through a 180-nm CMOS process and consumes 86mW at a 2Gb/s data rate, 1.8V supply.

Original language	English
Title of host publication	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	311-312
Number of pages	2
ISBN (Electronic)	9781728124780
DOIs	https://doi.org/10.1109/ISOCC47750.2019.9078519
State	Published - Oct 2019
Event	16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of Duration: 6 Oct 2019 → 9 Oct 2019

Publication series

Name	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Volume	2019-January

Conference

Conference	16th International System-on-Chip Design Conference, ISOCC 2019
Country/Territory	Korea, Republic of
City	Jeju
Period	6/10/19 → 9/10/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

Eye-open monitor
eye-diagram
optimal sampling point

Access to Document

10.1109/ISOCC47750.2019.9078519

Cite this

Son, K. S., Kim, N., & Kang, J. K. (2019). Counter-based Eye-open Monitoring System Design for High-speed Serial Interface. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 311-312). Article 9078519 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9078519

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keywords = "Eye-open monitor, eye-diagram, optimal sampling point",

author = "Son, {Kyung Sub} and Namyong Kim and Kang, {Jin Ku}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International System-on-Chip Design Conference, ISOCC 2019 ; Conference date: 06-10-2019 Through 09-10-2019",

year = "2019",

month = oct,

doi = "10.1109/ISOCC47750.2019.9078519",

language = "English",

series = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

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Son, KS, Kim, N & Kang, JK 2019, Counter-based Eye-open Monitoring System Design for High-speed Serial Interface. in Proceedings - 2019 International SoC Design Conference, ISOCC 2019., 9078519, Proceedings - 2019 International SoC Design Conference, ISOCC 2019, vol. 2019-January, Institute of Electrical and Electronics Engineers Inc., pp. 311-312, 16th International System-on-Chip Design Conference, ISOCC 2019, Jeju, Korea, Republic of, 6/10/19. https://doi.org/10.1109/ISOCC47750.2019.9078519

Counter-based Eye-open Monitoring System Design for High-speed Serial Interface. / Son, Kyung Sub; Kim, Namyong; Kang, Jin Ku.
Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 311-312 9078519 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Abstract-An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. Through the estimated eye-opening information, the eye calculates the open area and the optimal sampling point. The size and phase of the sampling point are controlled by 5-bit, respectively. The proposed eye-open monitor was fabricated through a 180-nm CMOS process and consumes 86mW at a 2Gb/s data rate, 1.8V supply.

AB - Abstract-An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. Through the estimated eye-opening information, the eye calculates the open area and the optimal sampling point. The size and phase of the sampling point are controlled by 5-bit, respectively. The proposed eye-open monitor was fabricated through a 180-nm CMOS process and consumes 86mW at a 2Gb/s data rate, 1.8V supply.

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KW - optimal sampling point

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BT - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 6 October 2019 through 9 October 2019

ER -

Counter-based Eye-open Monitoring System Design for High-speed Serial Interface

Abstract

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Bibliographical note

Keywords

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