Abstract
A clock and data recovery circuit with a two exclusive-OR phase-frequency detector is proposed. The PFD generates the control signal for the voltage-controlled oscillator (VCO) in the phase-locked loop by comparing different phase clocks and input data. Simulations show that this circuit operates an input at data rate of 800 Mbit/ps to 1.2 Gbit/s under 2.5 V using 0.25 μm CMOS technology.
| Original language | English |
|---|---|
| Pages (from-to) | 1347-1349 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 36 |
| Issue number | 16 |
| DOIs | |
| State | Published - 3 Aug 2000 |