Channel-Stacked NAND Flash Memory with Tied Bit-Line and Ground Select Transistor

In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed structure can maximize memory density, since additional SSTs are not required for layer selection and the placement of BLs/word lines is similar to that of the conventional NAND array except for island-type GSTs. Basic memory operations are performed with fabricated devices. The selected layer is erased only by applying erase voltage to the selected common source line (CSL) and by biasing inhibition voltage to other CSLs. Only the selected layer is read by applying the same voltage as BL voltage to the CSLs of the unselected layers. In addition, the selected strings in the selected layer are programmed and other strings in the selected and unselected layers are all inhibited by the combination of CSL and BL voltages. Consequently, stable memory operations are obtained successfully in the proposed structure without interference between stacked layers.