Challenges in implementing high-k dielectrics in the 45nm technology node

B. H. Lee; S. C. Song; R. Choi; H. C. Wen; P. Majhi; P. Kirsch; C. Young; G. Bersuker

doi:10.1109/icicdt.2005.1502595

Challenges in implementing high-k dielectrics in the 45nm technology node

B. H. Lee, S. C. Song, R. Choi, H. C. Wen, P. Majhi, P. Kirsch, C. Young, G. Bersuker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.

Original language	English
Title of host publication	2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	73-76
Number of pages	4
ISBN (Print)	0780390814, 9780780390812
DOIs	https://doi.org/10.1109/icicdt.2005.1502595
State	Published - 2005
Externally published	Yes
Event	2005 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States Duration: 9 May 2005 → 11 May 2005

Publication series

Name	2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

Conference	2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin, TX
Period	9/05/05 → 11/05/05

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10.1109/icicdt.2005.1502595

Cite this

Lee, B. H., Song, S. C., Choi, R., Wen, H. C., Majhi, P., Kirsch, P., Young, C., & Bersuker, G. (2005). Challenges in implementing high-k dielectrics in the 45nm technology node. In 2005 International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 73-76). Article D2 (2005 International Conference on Integrated Circuit Design and Technology, ICICDT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/icicdt.2005.1502595

@inproceedings{b0f40208206f4d5d95252de7a5013102,

title = "Challenges in implementing high-k dielectrics in the 45nm technology node",

abstract = "Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.",

author = "Lee, {B. H.} and Song, {S. C.} and R. Choi and Wen, {H. C.} and P. Majhi and P. Kirsch and C. Young and G. Bersuker",

year = "2005",

doi = "10.1109/icicdt.2005.1502595",

language = "English",

isbn = "0780390814",

series = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "73--76",

booktitle = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT",

address = "United States",

note = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 09-05-2005 Through 11-05-2005",

}

Lee, BH, Song, SC, Choi, R, Wen, HC, Majhi, P, Kirsch, P, Young, C & Bersuker, G 2005, Challenges in implementing high-k dielectrics in the 45nm technology node. in 2005 International Conference on Integrated Circuit Design and Technology, ICICDT., D2, 2005 International Conference on Integrated Circuit Design and Technology, ICICDT, Institute of Electrical and Electronics Engineers Inc., pp. 73-76, 2005 International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 9/05/05. https://doi.org/10.1109/icicdt.2005.1502595

Challenges in implementing high-k dielectrics in the 45nm technology node. / Lee, B. H.; Song, S. C.; Choi, R. et al.
2005 International Conference on Integrated Circuit Design and Technology, ICICDT. Institute of Electrical and Electronics Engineers Inc., 2005. p. 73-76 D2 (2005 International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Challenges in implementing high-k dielectrics in the 45nm technology node

AU - Lee, B. H.

AU - Song, S. C.

AU - Choi, R.

AU - Wen, H. C.

AU - Majhi, P.

AU - Kirsch, P.

AU - Young, C.

AU - Bersuker, G.

PY - 2005

Y1 - 2005

N2 - Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.

AB - Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.

UR - http://www.scopus.com/inward/record.url?scp=25844484118&partnerID=8YFLogxK

U2 - 10.1109/icicdt.2005.1502595

DO - 10.1109/icicdt.2005.1502595

M3 - Conference contribution

AN - SCOPUS:25844484118

SN - 0780390814

SN - 9780780390812

T3 - 2005 International Conference on Integrated Circuit Design and Technology, ICICDT

SP - 73

EP - 76

BT - 2005 International Conference on Integrated Circuit Design and Technology, ICICDT

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Y2 - 9 May 2005 through 11 May 2005

ER -

Lee BH, Song SC, Choi R, Wen HC, Majhi P, Kirsch P et al. Challenges in implementing high-k dielectrics in the 45nm technology node. In 2005 International Conference on Integrated Circuit Design and Technology, ICICDT. Institute of Electrical and Electronics Engineers Inc. 2005. p. 73-76. D2. (2005 International Conference on Integrated Circuit Design and Technology, ICICDT). doi: 10.1109/icicdt.2005.1502595

Challenges in implementing high-k dielectrics in the 45nm technology node

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