Abstract
In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear {C} - {V} characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.
Original language | English |
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Pages (from-to) | 549-552 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 43 |
Issue number | 4 |
DOIs | |
State | Published - 1 Apr 2022 |
Bibliographical note
Publisher Copyright:© 1980-2012 IEEE.
Keywords
- Capacitor-based synaptic device
- MOS capacitor
- NAND flash memory
- capacitive neural network
- neuromorphic system
- spiking neural network (SNN)