An FPGA Implementation of CNN-based Compression Artifact Reduction

Jaemyung Kim; Jin Ku Kang; Yongwoo Kim

doi:10.1109/ISOCC56007.2022.10031558

An FPGA Implementation of CNN-based Compression Artifact Reduction

Jaemyung Kim, Jin Ku Kang, Yongwoo Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes a convolutional neural network (CNN) based compression artifact reduction hardware. The proposed CNN architecture is applied to re-parameterization and INT8 quantization methods for efficient inference in edge devices. As a result of applying the optimization methods, the model size was reduced by \times 5.62, and the number of operations was reduced by \times 1.72. The proposed hardware achieves a frame rate of 33.33 FPS when implemented on a Xilinx ZCU104 SoC.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	95-96
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031558
State	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 19 Oct 2022 → 22 Oct 2022

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	19/10/22 → 22/10/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

Compression Artifact Reduction
Convolutional Neural Network
FPGA

Access to Document

10.1109/ISOCC56007.2022.10031558

Cite this

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title = "An FPGA Implementation of CNN-based Compression Artifact Reduction",

abstract = "This paper proposes a convolutional neural network (CNN) based compression artifact reduction hardware. The proposed CNN architecture is applied to re-parameterization and INT8 quantization methods for efficient inference in edge devices. As a result of applying the optimization methods, the model size was reduced by \times 5.62, and the number of operations was reduced by \times 1.72. The proposed hardware achieves a frame rate of 33.33 FPS when implemented on a Xilinx ZCU104 SoC.",

keywords = "Compression Artifact Reduction, Convolutional Neural Network, FPGA",

author = "Jaemyung Kim and Kang, {Jin Ku} and Yongwoo Kim",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

year = "2022",

doi = "10.1109/ISOCC56007.2022.10031558",

language = "English",

series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "95--96",

booktitle = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

address = "United States",

}

Kim, J, Kang, JK & Kim, Y 2022, An FPGA Implementation of CNN-based Compression Artifact Reduction. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 95-96, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 19/10/22. https://doi.org/10.1109/ISOCC56007.2022.10031558

An FPGA Implementation of CNN-based Compression Artifact Reduction. / Kim, Jaemyung; Kang, Jin Ku; Kim, Yongwoo.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 95-96 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An FPGA Implementation of CNN-based Compression Artifact Reduction

AU - Kim, Jaemyung

AU - Kang, Jin Ku

AU - Kim, Yongwoo

PY - 2022

Y1 - 2022

N2 - This paper proposes a convolutional neural network (CNN) based compression artifact reduction hardware. The proposed CNN architecture is applied to re-parameterization and INT8 quantization methods for efficient inference in edge devices. As a result of applying the optimization methods, the model size was reduced by \times 5.62, and the number of operations was reduced by \times 1.72. The proposed hardware achieves a frame rate of 33.33 FPS when implemented on a Xilinx ZCU104 SoC.

AB - This paper proposes a convolutional neural network (CNN) based compression artifact reduction hardware. The proposed CNN architecture is applied to re-parameterization and INT8 quantization methods for efficient inference in edge devices. As a result of applying the optimization methods, the model size was reduced by \times 5.62, and the number of operations was reduced by \times 1.72. The proposed hardware achieves a frame rate of 33.33 FPS when implemented on a Xilinx ZCU104 SoC.

KW - Compression Artifact Reduction

KW - Convolutional Neural Network

KW - FPGA

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U2 - 10.1109/ISOCC56007.2022.10031558

DO - 10.1109/ISOCC56007.2022.10031558

M3 - Conference contribution

AN - SCOPUS:85148427435

T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022

SP - 95

EP - 96

BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

Y2 - 19 October 2022 through 22 October 2022

ER -

An FPGA Implementation of CNN-based Compression Artifact Reduction

Abstract

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Bibliographical note

Keywords

Access to Document

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