All digital DLL with three phase timing stages

Jin Ho Choi; Jin Ku Kang

All digital DLL with three phase timing stages

Inha University

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 μm CMOS technology under 3.3V power supply. The simulation result shows the maximum phase error can be reduced to 13-42ps with the operating range of 250 MHz to 800 MHz.

Original language	English
Pages (from-to)	1305-1309
Number of pages	5
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E87-A
Issue number	6
State	Published - Jun 2004

Keywords

All digital DLL
CMOS
Phase error
Phase resolution

Cite this

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abstract = "This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 μm CMOS technology under 3.3V power supply. The simulation result shows the maximum phase error can be reduced to 13-42ps with the operating range of 250 MHz to 800 MHz.",

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AB - This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 μm CMOS technology under 3.3V power supply. The simulation result shows the maximum phase error can be reduced to 13-42ps with the operating range of 250 MHz to 800 MHz.

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All digital DLL with three phase timing stages

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Keywords

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