A Wide-range Low Power Quarter Rate Single Loop CDR

Jin Ho Kim; Jin Ku Kang

doi:10.1109/ISOCC56007.2022.10031567

A Wide-range Low Power Quarter Rate Single Loop CDR

Jin Ho Kim
, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a reference-less single loop clock and data recovery circuit (CDR). The proposed CDR is operating with unlimited capture range. And problem generated by oversampling is removed using bang-bang phase detector (BBPD) with two samples per 1UI. Simulation result shows the proposed CDR achieves a wide capture range from 2.6Gb/s to 13.2Gb/s and power consumption is 0.363 [pJ/bit] at 13.2Gb/s. This work is designed using 28nm CMOS process.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	145-146
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031567
State	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 19 Oct 2022 → 22 Oct 2022

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	19/10/22 → 22/10/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

Bang-bang phase detector (BBPD)
Quarter rate CDR
Single Loop CDR
Unlimited capture range

Access to Document

10.1109/ISOCC56007.2022.10031567

Cite this

@inproceedings{411203ed8fcd43be997b8afebb953e31,

title = "A Wide-range Low Power Quarter Rate Single Loop CDR",

abstract = "This paper presents a reference-less single loop clock and data recovery circuit (CDR). The proposed CDR is operating with unlimited capture range. And problem generated by oversampling is removed using bang-bang phase detector (BBPD) with two samples per 1UI. Simulation result shows the proposed CDR achieves a wide capture range from 2.6Gb/s to 13.2Gb/s and power consumption is 0.363 [pJ/bit] at 13.2Gb/s. This work is designed using 28nm CMOS process.",

keywords = "Bang-bang phase detector (BBPD), Quarter rate CDR, Single Loop CDR, Unlimited capture range",

author = "Kim, \{Jin Ho\} and Kang, \{Jin Ku\}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

year = "2022",

doi = "10.1109/ISOCC56007.2022.10031567",

language = "English",

series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "145--146",

booktitle = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

address = "United States",

}

Kim, JH & Kang, JK 2022, A Wide-range Low Power Quarter Rate Single Loop CDR. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 145-146, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 19/10/22. https://doi.org/10.1109/ISOCC56007.2022.10031567

A Wide-range Low Power Quarter Rate Single Loop CDR. / Kim, Jin Ho; Kang, Jin Ku.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 145-146 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Wide-range Low Power Quarter Rate Single Loop CDR

AU - Kim, Jin Ho

AU - Kang, Jin Ku

PY - 2022

Y1 - 2022

N2 - This paper presents a reference-less single loop clock and data recovery circuit (CDR). The proposed CDR is operating with unlimited capture range. And problem generated by oversampling is removed using bang-bang phase detector (BBPD) with two samples per 1UI. Simulation result shows the proposed CDR achieves a wide capture range from 2.6Gb/s to 13.2Gb/s and power consumption is 0.363 [pJ/bit] at 13.2Gb/s. This work is designed using 28nm CMOS process.

AB - This paper presents a reference-less single loop clock and data recovery circuit (CDR). The proposed CDR is operating with unlimited capture range. And problem generated by oversampling is removed using bang-bang phase detector (BBPD) with two samples per 1UI. Simulation result shows the proposed CDR achieves a wide capture range from 2.6Gb/s to 13.2Gb/s and power consumption is 0.363 [pJ/bit] at 13.2Gb/s. This work is designed using 28nm CMOS process.

KW - Bang-bang phase detector (BBPD)

KW - Quarter rate CDR

KW - Single Loop CDR

KW - Unlimited capture range

UR - https://www.scopus.com/pages/publications/85148444152

U2 - 10.1109/ISOCC56007.2022.10031567

DO - 10.1109/ISOCC56007.2022.10031567

M3 - Conference contribution

AN - SCOPUS:85148444152

T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022

SP - 145

EP - 146

BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

Y2 - 19 October 2022 through 22 October 2022

ER -

A Wide-range Low Power Quarter Rate Single Loop CDR

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this