A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique

Majid Jalalifar, Gyung Su Byun

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A phase-locked loop (PLL) along with a linear phase interpolator that generates 64 phases with low jitter in a continuous lock range of 400 MHz-2.2 GHz for mobile memory interfaces is presented. To provide adaptive and precise phase interpolation (PI), a novel frequency tracking PI bias along with a wide-frequency range PLL and lock-detection control are employed. The PLL-based PI is fabricated in 65-nm CMOS and achieves a peak-to-peak and an RMS jitter of 14.8 ps and 2.16 ps, respectively. The measured DNL and INL of the proposed PI are 0.21 LSB and 0.43 LSB, respectively. The PLL-based PI consumes 8.1 mW at a 1.0-V supply.

Original languageEnglish
Pages (from-to)903-907
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number7
DOIs
StatePublished - Jul 2018

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

  • Phase-locked loop
  • VCO
  • memory interface
  • phase interpolator

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