Abstract
Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurred in the transmission process. This paper presents a VLSI implementation of a high-speed 8-error correcting RS(255,239) decoder architecture using modified Euclidean algorithm for the communication systems. The RS decoder has been designed and implemented with the 0.16-μm CMOS standard cell technology with a supply voltage of 1.5V. The results show that the proposed RS decoder operates at a clock frequency of 670 MHz and has a data processing rate of 5.36 Gbits/s.
| Original language | English |
|---|---|
| Pages (from-to) | 316-320 |
| Number of pages | 5 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| State | Published - 2001 |
| Externally published | Yes |
| Event | 14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States Duration: 12 Sep 2001 → 15 Sep 2001 |