A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier

Min Kim; Kyung Sub Son; Namhoon Kim; Chang Hang Rho; Jin Ku Kang

doi:10.1109/ISOCC.2018.8649906

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier

Min Kim, Kyung Sub Son, Namhoon Kim, Chang Hang Rho, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

A two-step time-to-digital converter using a ring oscillator time amplifier is presented. The time amplifier structure does not accumulates the error in the iterative process of time. There are 8 bits in total, of which 4 bits are obtained in the coarse conversion and 4 bits are obtained in the fine conversion by amplifying the remaining time. The TDC circuit occupied an area of 0.34 mm² using 180 nm CMOS process. The effective number of bits is 7.42bits. The TDC circuit has shown 10.5 ps resolution for a 50 MHz. The DNL and INL are 0.7(LSB) and 0.5(LSB), respectively. The power consumption is 1.34 mW with a 1.8 V supply.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2018, ISOCC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	143-144
Number of pages	2
ISBN (Electronic)	9781538679609
DOIs	https://doi.org/10.1109/ISOCC.2018.8649906
State	Published - 2 Jul 2018
Event	15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of Duration: 12 Nov 2018 → 15 Nov 2018

Publication series

Name	Proceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference	15th International SoC Design Conference, ISOCC 2018
Country/Territory	Korea, Republic of
City	Daegu
Period	12/11/18 → 15/11/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

DPLL (Digital-Phase locked loop)
TDC (Time-to-Digital Converter)
Two-Step TDC

Access to Document

10.1109/ISOCC.2018.8649906

Cite this

Kim, M., Son, K. S., Kim, N., Rho, C. H., & Kang, J. K. (2018). A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 143-144). Article 8649906 (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649906

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title = "A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier",

abstract = "A two-step time-to-digital converter using a ring oscillator time amplifier is presented. The time amplifier structure does not accumulates the error in the iterative process of time. There are 8 bits in total, of which 4 bits are obtained in the coarse conversion and 4 bits are obtained in the fine conversion by amplifying the remaining time. The TDC circuit occupied an area of 0.34 mm2 using 180 nm CMOS process. The effective number of bits is 7.42bits. The TDC circuit has shown 10.5 ps resolution for a 50 MHz. The DNL and INL are 0.7(LSB) and 0.5(LSB), respectively. The power consumption is 1.34 mW with a 1.8 V supply.",

keywords = "DPLL (Digital-Phase locked loop), TDC (Time-to-Digital Converter), Two-Step TDC",

author = "Min Kim and Son, {Kyung Sub} and Namhoon Kim and Rho, {Chang Hang} and Kang, {Jin Ku}",

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year = "2018",

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doi = "10.1109/ISOCC.2018.8649906",

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Kim, M, Son, KS, Kim, N, Rho, CH & Kang, JK 2018, A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649906, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 143-144, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 12/11/18. https://doi.org/10.1109/ISOCC.2018.8649906

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. / Kim, Min; Son, Kyung Sub; Kim, Namhoon et al.
Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 143-144 8649906 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Son, Kyung Sub

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AU - Rho, Chang Hang

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PY - 2018/7/2

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N2 - A two-step time-to-digital converter using a ring oscillator time amplifier is presented. The time amplifier structure does not accumulates the error in the iterative process of time. There are 8 bits in total, of which 4 bits are obtained in the coarse conversion and 4 bits are obtained in the fine conversion by amplifying the remaining time. The TDC circuit occupied an area of 0.34 mm2 using 180 nm CMOS process. The effective number of bits is 7.42bits. The TDC circuit has shown 10.5 ps resolution for a 50 MHz. The DNL and INL are 0.7(LSB) and 0.5(LSB), respectively. The power consumption is 1.34 mW with a 1.8 V supply.

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KW - DPLL (Digital-Phase locked loop)

KW - TDC (Time-to-Digital Converter)

KW - Two-Step TDC

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A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier

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Bibliographical note

Keywords

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