A power-aware variable-precision multiply-accumulate unit

Jin Kyu Chang, Hanho Lee, Chang Seok Choi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

An energy-efficient power-aware design is highly desirable for digital signal processing (DSP) functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this paper presents a power-aware variable-precision multiply-accumulate (VP-MAC) unit that makes use of dynamic-range detection unit and a 16-bit scalable Baugh-Wooley Multiplier with fixed-width error compensation circuit for DSP applications. The proposed VP-MAC contains both an 8-bit and a 16-bit multiplier and has input gating to route the data to appropriate hardware. When 16-bit multiplication is needed, the entire multiplier is used. However, if only 8-bit multiplication is needed, the 8-bit logic is enabled. Simulated and measured results show a reduced power-consumption of 43% and reduced gate count of 42.7% respectively, in comparison with conventional power-aware scalable pipelined MAC unit.

Original languageEnglish
Title of host publication2009 9th International Symposium on Communications and Information Technology, ISCIT 2009
Pages1336-1339
Number of pages4
DOIs
StatePublished - 2009
Event2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 - Icheon, Korea, Republic of
Duration: 28 Sep 200930 Sep 2009

Publication series

Name2009 9th International Symposium on Communications and Information Technology, ISCIT 2009

Conference

Conference2009 9th International Symposium on Communications and Information Technology, ISCIT 2009
Country/TerritoryKorea, Republic of
CityIcheon
Period28/09/0930/09/09

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