A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

Eunho Yang; Kyongsu Lee; Jin Ku Kang

doi:10.1109/ISCAS.2015.7168641

A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

Eunho Yang, Kyongsu Lee, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format.

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	345-348
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7168641
State	Published - 27 Jul 2015
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	24/05/15 → 27/05/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

MIPI M-PHY
Pulse width modulation (PWM)
clock and data recovery (CDR)
low voltage differential signal (LVDS)

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10.1109/ISCAS.2015.7168641

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Yang, E., Lee, K., & Kang, J. K. (2015). A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 345-348). Article 7168641 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168641

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abstract = "This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format.",

keywords = "MIPI M-PHY, Pulse width modulation (PWM), clock and data recovery (CDR), low voltage differential signal (LVDS)",

author = "Eunho Yang and Kyongsu Lee and Kang, {Jin Ku}",

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doi = "10.1109/ISCAS.2015.7168641",

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Yang, E, Lee, K & Kang, JK 2015, A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7168641, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 345-348, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7168641

A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme. / Yang, Eunho; Lee, Kyongsu; Kang, Jin Ku.
2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 345-348 7168641 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kang, Jin Ku

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N2 - This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format.

AB - This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format.

KW - MIPI M-PHY

KW - Pulse width modulation (PWM)

KW - clock and data recovery (CDR)

KW - low voltage differential signal (LVDS)

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A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

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