Abstract
This paper presents a high-speed low-complexity Reed–Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-μm CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.
| Original language | English |
|---|---|
| Pages (from-to) | 461-465 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 52 |
| Issue number | 8 |
| DOIs | |
| State | Published - Aug 2005 |
Bibliographical note
Funding Information:Manuscript received July 30, 2004. This work was supported by Inha UWB-RC, Korea. This paper was recommended by Associate Editor A. Apsel. The author is with the School of Information and Communication Engineering, Inha University, Incheon, 402–751, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSII.2005.850452
Keywords
- Forward error correction (FEC)
- Reed-Solomon (RS) coding
- high speed
- low complexity
- modified Euclidean algorithm
- optical communications
- pipelined
- recursive