Abstract
This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (Dual-pSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. Two-parallel processing allows the decoder to achieve a high data processing rate required for 100 Gb/s optical communication systems. Also, the proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10 -15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.
Original language | English |
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Pages (from-to) | 43-55 |
Number of pages | 13 |
Journal | Journal of Signal Processing Systems |
Volume | 66 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2012 |
Bibliographical note
Funding Information:Acknowledgement This research was partly supported by the IT R&D program of the MKE/MKIT [2010-F-010-01] and partly supported by the MKE, Korea, under the ITRC support program supervised by the NIPA (NIPA-2010-C1090-1011-0007)
Keywords
- 100G
- BCH codes
- Concatenated codes
- Decoder
- FEC
- Low complexity