A design of displayport link layer

Yong Woo Kim; Seong Bok Cha; Jin Ku Kang

doi:10.1109/SOCDC.2008.4815680

A design of displayport link layer

Yong Woo Kim, Seong Bok Cha, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents an implementation of DisplayPort 1.1 Link Layer. The DisplayPort link layer provides isochronous transport service, link service, and device service. Isochronous transport service in source device maps the video and audio streams into the main link under a set of rules, so that the stream can be properly reconstructed to original format and synchronized by the sink device. The link service is used for discovering, configuring, and maintaining the link by accessing DPCD via AUX CH. The main link transmitter and receiver is implemented with 4,820 ALUTs and 4496 register, 557,110 of block memory bits synthesized using Quartus II at Altera Stratix II GX board and can be operated at 200.32MHz. Also, the AUXCH block is implemented with 765 ALUTs and 298 register, respectively.

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Pages	II45-II48
DOIs	https://doi.org/10.1109/SOCDC.2008.4815680
State	Published - 2008
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 24 Nov 2008 → 25 Nov 2008

Publication series

Name	2008 International SoC Design Conference, ISOCC 2008
Volume	2

Conference

Conference	2008 International SoC Design Conference, ISOCC 2008
Country/Territory	Korea, Republic of
City	Busan
Period	24/11/08 → 25/11/08

Keywords

ANSI 8B/10B
AUXCH
DPCD
Keywords-displayport
Link layer
Mainlink
Physical layer

Access to Document

10.1109/SOCDC.2008.4815680

Cite this

@inproceedings{a893a0dfcd074f4ba297d903e6bf1b90,

title = "A design of displayport link layer",

abstract = "This paper presents an implementation of DisplayPort 1.1 Link Layer. The DisplayPort link layer provides isochronous transport service, link service, and device service. Isochronous transport service in source device maps the video and audio streams into the main link under a set of rules, so that the stream can be properly reconstructed to original format and synchronized by the sink device. The link service is used for discovering, configuring, and maintaining the link by accessing DPCD via AUX CH. The main link transmitter and receiver is implemented with 4,820 ALUTs and 4496 register, 557,110 of block memory bits synthesized using Quartus II at Altera Stratix II GX board and can be operated at 200.32MHz. Also, the AUXCH block is implemented with 765 ALUTs and 298 register, respectively.",

keywords = "ANSI 8B/10B, AUXCH, DPCD, Keywords-displayport, Link layer, Mainlink, Physical layer",

author = "Kim, {Yong Woo} and Cha, {Seong Bok} and Kang, {Jin Ku}",

year = "2008",

doi = "10.1109/SOCDC.2008.4815680",

language = "English",

isbn = "9781424425990",

series = "2008 International SoC Design Conference, ISOCC 2008",

pages = "II45--II48",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",

}

TY - GEN

T1 - A design of displayport link layer

AU - Kim, Yong Woo

AU - Cha, Seong Bok

AU - Kang, Jin Ku

PY - 2008

Y1 - 2008

N2 - This paper presents an implementation of DisplayPort 1.1 Link Layer. The DisplayPort link layer provides isochronous transport service, link service, and device service. Isochronous transport service in source device maps the video and audio streams into the main link under a set of rules, so that the stream can be properly reconstructed to original format and synchronized by the sink device. The link service is used for discovering, configuring, and maintaining the link by accessing DPCD via AUX CH. The main link transmitter and receiver is implemented with 4,820 ALUTs and 4496 register, 557,110 of block memory bits synthesized using Quartus II at Altera Stratix II GX board and can be operated at 200.32MHz. Also, the AUXCH block is implemented with 765 ALUTs and 298 register, respectively.

AB - This paper presents an implementation of DisplayPort 1.1 Link Layer. The DisplayPort link layer provides isochronous transport service, link service, and device service. Isochronous transport service in source device maps the video and audio streams into the main link under a set of rules, so that the stream can be properly reconstructed to original format and synchronized by the sink device. The link service is used for discovering, configuring, and maintaining the link by accessing DPCD via AUX CH. The main link transmitter and receiver is implemented with 4,820 ALUTs and 4496 register, 557,110 of block memory bits synthesized using Quartus II at Altera Stratix II GX board and can be operated at 200.32MHz. Also, the AUXCH block is implemented with 765 ALUTs and 298 register, respectively.

KW - ANSI 8B/10B

KW - AUXCH

KW - DPCD

KW - Keywords-displayport

KW - Link layer

KW - Mainlink

KW - Physical layer

UR - http://www.scopus.com/inward/record.url?scp=67650677397&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2008.4815680

DO - 10.1109/SOCDC.2008.4815680

M3 - Conference contribution

AN - SCOPUS:67650677397

SN - 9781424425990

T3 - 2008 International SoC Design Conference, ISOCC 2008

SP - II45-II48

BT - 2008 International SoC Design Conference, ISOCC 2008

T2 - 2008 International SoC Design Conference, ISOCC 2008

Y2 - 24 November 2008 through 25 November 2008

ER -

A design of displayport link layer

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this