@inproceedings{f966c313f4594a5aaa89327e9fd6ca06,
title = "A CMOS clock and data recovery with two-XOR phase-frequency detector circuit",
abstract = "This paper describes a 1.0 Gbps Clock and Data Recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m-CMOS HSPICE simulation. The circuit is under fabrication. The measured results are presented.",
author = "Kang, {Jin Ku} and Kim, {Dong Hee}",
year = "2001",
doi = "10.1109/ISCAS.2001.922223",
language = "English",
isbn = "0780366859",
series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",
pages = "266--269",
booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",
note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",
}