@inproceedings{fe932efccdad4f36ac24f6c745a1fdde,
title = "A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-μm CMOS",
abstract = "The rapid growth of the data rate in serial links reveals the problem of power consumption, motivating utilization of low power building blocks. This paper presents a low-power clock and data recovery (CDR). By employing dynamic CML latch which draws a current during half of the clock cycle and voltage-to-current(V/I) converter which performs the XOR function itself, power reduction in phase detector(PD) is achieved. The CDR circuit is simulated using 5-Gb/s data with 0.18-μm CMOS technology, and the circuit consumes 8.7mW from a 1.8-V supply.",
keywords = "Clock and Data Recovery(CDR), half-rate linear phase detector(PD)",
author = "An, {Taek Joon} and Son, {Kyung Sub} and Kim, {Young Jin} and Kong, {In Seok} and Kang, {Jin Ku}",
year = "2014",
doi = "10.1109/ISCAS.2014.6865638",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2329--2332",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",
note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",
}