@inproceedings{3e69d78151e34da6adc88c912952edcd,
title = "A 5-Gb/s 11.4mW half-rate CDR in 0.18μm CMOS",
abstract = "A low-power clock and data recovery(CDR) circuit with a phase detector(PD) using dynamic current-mode logic latches and a novel V/I converter is described. The proposed latch draws a current during half of the clock cycle and the proposed V/I converter includes the XOR function by itself. The half-rate CDR circuit is simulated using 5-Gb/s with 0.18-um CMOS technology, and the circuit consumes only 11.4mW from a 1.8-V supply.",
keywords = "Clock and Data Recovery(CDR), half-rate linear phase detector(PD)",
author = "An, {Taek Joon} and Kang, {Jin Ku}",
year = "2013",
doi = "10.1109/ISOCC.2013.6864042",
language = "English",
isbn = "9781479911417",
series = "ISOCC 2013 - 2013 International SoC Design Conference",
publisher = "IEEE Computer Society",
pages = "333--334",
booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",
address = "United States",
note = "2013 International SoC Design Conference, ISOCC 2013 ; Conference date: 17-11-2013 Through 19-11-2013",
}