A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

Tae Ho Kim; Jong Seok Han; Sang Soon Im; Jae Young Jang; Jin Ku Kang

doi:10.1109/ESSCIRC.2011.6044979

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

Tae Ho Kim, Jong Seok Han, Sang Soon Im, Jae Young Jang, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm x 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

Original language	English
Title of host publication	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages	351-354
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6044979
State	Published - 2011
Event	37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland Duration: 12 Sep 2011 → 16 Sep 2011

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	37th European Solid-State Circuits Conference, ESSCIRC 2011
Country/Territory	Finland
City	Helsinki
Period	12/09/11 → 16/09/11

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10.1109/ESSCIRC.2011.6044979

Cite this

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title = "A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement",

abstract = "This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm x 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.",

author = "Kim, {Tae Ho} and Han, {Jong Seok} and Im, {Sang Soon} and Jang, {Jae Young} and Kang, {Jin Ku}",

year = "2011",

doi = "10.1109/ESSCIRC.2011.6044979",

language = "English",

isbn = "9781457707018",

series = "European Solid-State Circuits Conference",

pages = "351--354",

booktitle = "ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference",

note = "37th European Solid-State Circuits Conference, ESSCIRC 2011 ; Conference date: 12-09-2011 Through 16-09-2011",

}

Kim, TH, Han, JS, Im, SS, Jang, JY & Kang, JK 2011, A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6044979, European Solid-State Circuits Conference, pp. 351-354, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 12/09/11. https://doi.org/10.1109/ESSCIRC.2011.6044979

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. / Kim, Tae Ho; Han, Jong Seok; Im, Sang Soon et al.
ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 351-354 6044979 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kang, Jin Ku

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N2 - This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm x 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

AB - This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm x 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

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DO - 10.1109/ESSCIRC.2011.6044979

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T3 - European Solid-State Circuits Conference

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Y2 - 12 September 2011 through 16 September 2011

ER -

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

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