Abstract
A 5-bit highly-accurate, low-power, and high-performance three-dimensional (3D) flash analog to digital converter (ADC) is presented for communication system applications. This architecture implements very short vertical interconnections, namely through-silicon via (TSV) channels to improve dynamic performance, increase power efficiency, and decrease the silicon area. To validate the proposed 3D flash ADC design, the architecture is simulated in a 65 nm CMOS technology. The 3D TSV channels (i.e., TSV and μbumps) are modeled to generate S-parameters using a 3D EM solver tool (i.e., HFSS). The demonstrated results reveal that the whole structure achieves SFDR of 39.8 and power consumption of 5.4 at 400 MS/s sampling rate.
Original language | English |
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Title of host publication | 2018 IEEE 8th Annual Computing and Communication Workshop and Conference, CCWC 2018 |
Editors | Satyajit Chakrabarti, Himadri Nath Saha |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 956-958 |
Number of pages | 3 |
ISBN (Electronic) | 9781538646496 |
DOIs | |
State | Published - 22 Feb 2018 |
Event | 8th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2018 - Las Vegas, United States Duration: 8 Jan 2018 → 10 Jan 2018 |
Publication series
Name | 2018 IEEE 8th Annual Computing and Communication Workshop and Conference, CCWC 2018 |
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Volume | 2018-January |
Conference
Conference | 8th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2018 |
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Country/Territory | United States |
City | Las Vegas |
Period | 8/01/18 → 10/01/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Keywords
- Flash analog to digital converter (ADC)
- data converter design
- three-dimensional (3D) IC design
- through-silicon-via (TSV)