A 3D flash ADC structure for high-speed communication applications

Nahid Mirzaie, Ahmed Alzahmi, Chung Ching Lin, Gyung Su Byun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A 5-bit highly-accurate, low-power, and high-performance three-dimensional (3D) flash analog to digital converter (ADC) is presented for communication system applications. This architecture implements very short vertical interconnections, namely through-silicon via (TSV) channels to improve dynamic performance, increase power efficiency, and decrease the silicon area. To validate the proposed 3D flash ADC design, the architecture is simulated in a 65 nm CMOS technology. The 3D TSV channels (i.e., TSV and μbumps) are modeled to generate S-parameters using a 3D EM solver tool (i.e., HFSS). The demonstrated results reveal that the whole structure achieves SFDR of 39.8 and power consumption of 5.4 at 400 MS/s sampling rate.

Original languageEnglish
Title of host publication2018 IEEE 8th Annual Computing and Communication Workshop and Conference, CCWC 2018
EditorsSatyajit Chakrabarti, Himadri Nath Saha
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages956-958
Number of pages3
ISBN (Electronic)9781538646496
DOIs
StatePublished - 22 Feb 2018
Event8th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2018 - Las Vegas, United States
Duration: 8 Jan 201810 Jan 2018

Publication series

Name2018 IEEE 8th Annual Computing and Communication Workshop and Conference, CCWC 2018
Volume2018-January

Conference

Conference8th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2018
Country/TerritoryUnited States
CityLas Vegas
Period8/01/1810/01/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

  • Flash analog to digital converter (ADC)
  • data converter design
  • three-dimensional (3D) IC design
  • through-silicon-via (TSV)

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