@inproceedings{33a537a82592476180304a2a499773a0,
title = "A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for display port",
abstract = "This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a {"}Mode{"} switch control. This work is implemented 0.18μm CMOS process. The device exhibits peak-to-peak jitters of 12ps and 14ps in the recovered clock with random data inputs. The power dissipation is 81mW from a 1.8V supply.",
keywords = "Clock and data recovery (CDR), Displayport, Voltage-controlled oscillator (VCO), half-rate phase detector (PD)",
author = "Seungwon Lee and Yoo, {Jae Wook} and Kang, {Jin Ku}",
year = "2008",
doi = "10.1109/SOCDC.2008.4815672",
language = "English",
isbn = "9781424425990",
series = "2008 International SoC Design Conference, ISOCC 2008",
pages = "II13--II16",
booktitle = "2008 International SoC Design Conference, ISOCC 2008",
note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",
}