A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18um CMOS

Seungwon Lee; Tae Ho Kim; Jae Wook Yoo; Jin Ku Kang

doi:10.1109/SOCCON.2009.5398064

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18um CMOS

Seungwon Lee, Tae Ho Kim, Jae Wook Yoo, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2009
Pages	179-182
Number of pages	4
DOIs	https://doi.org/10.1109/SOCCON.2009.5398064
State	Published - 2009
Event	IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland Duration: 9 Sep 2009 → 11 Sep 2009

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2009

Conference

Conference	IEEE International SOC Conference, SOCC 2009
Country/Territory	Ireland
City	Belfast
Period	9/09/09 → 11/09/09

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10.1109/SOCCON.2009.5398064

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title = "A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18um CMOS",

abstract = "This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a {"}Mode{"} switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.",

author = "Seungwon Lee and Kim, {Tae Ho} and Yoo, {Jae Wook} and Kang, {Jin Ku}",

year = "2009",

doi = "10.1109/SOCCON.2009.5398064",

language = "English",

isbn = "9781424452200",

series = "Proceedings - IEEE International SOC Conference, SOCC 2009",

pages = "179--182",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2009",

note = "IEEE International SOC Conference, SOCC 2009 ; Conference date: 09-09-2009 Through 11-09-2009",

}

Lee, S, Kim, TH, Yoo, JW & Kang, JK 2009, A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18um CMOS. in Proceedings - IEEE International SOC Conference, SOCC 2009., 5398064, Proceedings - IEEE International SOC Conference, SOCC 2009, pp. 179-182, IEEE International SOC Conference, SOCC 2009, Belfast, Ireland, 9/09/09. https://doi.org/10.1109/SOCCON.2009.5398064

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18um CMOS. / Lee, Seungwon; Kim, Tae Ho; Yoo, Jae Wook et al.
Proceedings - IEEE International SOC Conference, SOCC 2009. 2009. p. 179-182 5398064 (Proceedings - IEEE International SOC Conference, SOCC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kang, Jin Ku

PY - 2009

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N2 - This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

AB - This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

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Y2 - 9 September 2009 through 11 September 2009

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A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18um CMOS

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