A 2.2-mW 20-135-MHz false-lock-free DLL for display interface in 0.15-μm CMOS

Yong Hwan Moon; In Seok Kong; Young Soo Ryu; Jin Ku Kang

doi:10.1109/TCSII.2014.2327338

A 2.2-mW 20-135-MHz false-lock-free DLL for display interface in 0.15-μm CMOS

Yong Hwan Moon, In Seok Kong, Young Soo Ryu, Jin Ku Kang

Research output: Contribution to journal › Article › peer-review

17 Scopus citations

Abstract

This brief describes a wide-range operating false-lock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.

Original language	English
Article number	6823172
Pages (from-to)	554-558
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	61
Issue number	8
DOIs	https://doi.org/10.1109/TCSII.2014.2327338
State	Published - 1 Aug 2014

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

Complementary metal-oxide-semiconductor (CMOS)
delay-locked loop (DLL)
display interface
false lock
harmonic lock

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10.1109/TCSII.2014.2327338

Cite this

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abstract = "This brief describes a wide-range operating false-lock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.",

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A 2.2-mW 20-135-MHz false-lock-free DLL for display interface in 0.15-μm CMOS

Abstract

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Keywords

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