A 1T-DRAM cell based on a tunnel field-effect transistor with highly-scalable pillar and surrounding gate structure

Hyungjin Kim, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this work, a 1-transistor (1T) dynamic random access memory (DRAM) cell based on a tunnel field-effect transistor (TFET) is introduced and its operation physics demonstrated. It is structurally based on a pillar structure and surrounding gate, which gives a high scalability compared with the conventional 1T-1 capacitor (1C) DRAM cell so it can be easily made into a 4F2 cell array. The program operation is performed not by hole generation through impact ionization or gate-induced drain leakage but by hole injection from the source region unlike other 1T DRAM cells. In addition, the tunneling current mechanism of the device gives low power consumption DRAM operation and good retention characteristics to the proposed device.

Original languageEnglish
Pages (from-to)323-327
Number of pages5
JournalJournal of the Korean Physical Society
Volume69
Issue number3
DOIs
StatePublished - 1 Aug 2016
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2016, The Korean Physical Society.

Keywords

  • 1T DRAM
  • Band-to-band tunneling
  • High scalability
  • Surrounding gate
  • Tunnel field-effect transistor

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