A 1.8V 700Mb/s/spin 512Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

C. Yoo; K. Kyung; G. H. Han; K. Lim; H. Lee; J. Chai; N. W. Heo; G. Byun; D. J. Lee; H. I. Choi; H. C. Choi; C. H. Kim; S. Cho

A 1.8V 700Mb/s/spin 512Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

C. Yoo, K. Kyung, G. H. Han, K. Lim, H. Lee, J. Chai, N. W. Heo, G. Byun, D. J. Lee, H. I. Choi, H. C. Choi, C. H. Kim, S. Cho

Samsung

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

A 1.8V 700Mb/s/pin 512Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, t_AA/t_RCD/t_RP of 3/3/3 at 533Mb/s are achieved in the design. For signal integrity at 533Mb/s, off-chip driver calibration and on-die termination are employed.

Original language	English
Pages (from-to)	299+312-313+495
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
State	Published - 2003
Externally published	Yes
Event	2003 Digest of Technical Papers - , United States Duration: 9 Feb 2003 → 13 Feb 2003

Cite this

@article{3a6c8c858d094fe5a1ceb13e82144890,

title = "A 1.8V 700Mb/s/spin 512Mb DDR-II SDRAM with on-die termination and off-chip driver calibration",

abstract = "A 1.8V 700Mb/s/pin 512Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, tAA/tRCD/tRP of 3/3/3 at 533Mb/s are achieved in the design. For signal integrity at 533Mb/s, off-chip driver calibration and on-die termination are employed.",

author = "C. Yoo and K. Kyung and Han, {G. H.} and K. Lim and H. Lee and J. Chai and Heo, {N. W.} and G. Byun and Lee, {D. J.} and Choi, {H. I.} and Choi, {H. C.} and Kim, {C. H.} and S. Cho",

year = "2003",

language = "English",

pages = "299+312--313+495",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2003 Digest of Technical Papers ; Conference date: 09-02-2003 Through 13-02-2003",

}

TY - JOUR

T1 - A 1.8V 700Mb/s/spin 512Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

AU - Yoo, C.

AU - Kyung, K.

AU - Han, G. H.

AU - Lim, K.

AU - Lee, H.

AU - Chai, J.

AU - Heo, N. W.

AU - Byun, G.

AU - Lee, D. J.

AU - Choi, H. I.

AU - Choi, H. C.

AU - Kim, C. H.

AU - Cho, S.

PY - 2003

Y1 - 2003

N2 - A 1.8V 700Mb/s/pin 512Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, tAA/tRCD/tRP of 3/3/3 at 533Mb/s are achieved in the design. For signal integrity at 533Mb/s, off-chip driver calibration and on-die termination are employed.

AB - A 1.8V 700Mb/s/pin 512Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, tAA/tRCD/tRP of 3/3/3 at 533Mb/s are achieved in the design. For signal integrity at 533Mb/s, off-chip driver calibration and on-die termination are employed.

UR - http://www.scopus.com/inward/record.url?scp=0037630803&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0037630803

SN - 0193-6530

SP - 299+312-313+495

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2003 Digest of Technical Papers

Y2 - 9 February 2003 through 13 February 2003

ER -

A 1.8V 700Mb/s/spin 512Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Abstract

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