A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

Jin Cheol Seo; Sang Soon Im; Kwan Yoon; Seung Wook Oh; Taek Joon An; Gi Yeol Bae; Jin Ku Kang

doi:10.1109/SOCC.2012.6398380

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

Jin Cheol Seo, Sang Soon Im, Kwan Yoon, Seung Wook Oh, Taek Joon An, Gi Yeol Bae, Jin Ku Kang

Inha University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 2³¹-1 PRBS is measured to 7/5.6/4.7ps_rms, respectively, while consuming 11mW with a 1.2V supply.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2012
Pages	57-60
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2012.6398380
State	Published - 2012
Event	25th IEEE International System-on-Chip Conference, SOCC 2012 - Niagara Falls, NY, United States Duration: 12 Sep 2012 → 14 Sep 2012

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	25th IEEE International System-on-Chip Conference, SOCC 2012
Country/Territory	United States
City	Niagara Falls, NY
Period	12/09/12 → 14/09/12

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10.1109/SOCC.2012.6398380

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title = "A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2",

abstract = "In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 231-1 PRBS is measured to 7/5.6/4.7psrms, respectively, while consuming 11mW with a 1.2V supply.",

author = "Seo, {Jin Cheol} and Im, {Sang Soon} and Kwan Yoon and Oh, {Seung Wook} and An, {Taek Joon} and Bae, {Gi Yeol} and Kang, {Jin Ku}",

year = "2012",

doi = "10.1109/SOCC.2012.6398380",

language = "English",

isbn = "9781467312950",

series = "International System on Chip Conference",

pages = "57--60",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2012",

note = "25th IEEE International System-on-Chip Conference, SOCC 2012 ; Conference date: 12-09-2012 Through 14-09-2012",

}

Seo, JC, Im, SS, Yoon, K, Oh, SW, An, TJ, Bae, GY & Kang, JK 2012, A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. in Proceedings - IEEE International SOC Conference, SOCC 2012., 6398380, International System on Chip Conference, pp. 57-60, 25th IEEE International System-on-Chip Conference, SOCC 2012, Niagara Falls, NY, United States, 12/09/12. https://doi.org/10.1109/SOCC.2012.6398380

TY - GEN

T1 - A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

AU - Seo, Jin Cheol

AU - Im, Sang Soon

AU - Yoon, Kwan

AU - Oh, Seung Wook

AU - An, Taek Joon

AU - Bae, Gi Yeol

AU - Kang, Jin Ku

PY - 2012

Y1 - 2012

N2 - In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 231-1 PRBS is measured to 7/5.6/4.7psrms, respectively, while consuming 11mW with a 1.2V supply.

AB - In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 231-1 PRBS is measured to 7/5.6/4.7psrms, respectively, while consuming 11mW with a 1.2V supply.

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U2 - 10.1109/SOCC.2012.6398380

DO - 10.1109/SOCC.2012.6398380

M3 - Conference contribution

AN - SCOPUS:84872530608

SN - 9781467312950

T3 - International System on Chip Conference

SP - 57

EP - 60

BT - Proceedings - IEEE International SOC Conference, SOCC 2012

T2 - 25th IEEE International System-on-Chip Conference, SOCC 2012

Y2 - 12 September 2012 through 14 September 2012

ER -

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

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