A 1.4Gb/s DLL using 2nd order charge-pump scheme for low phase/duty error for high-speed DRAM application

Kyu hyoun Kim; Jung Bae Lee; Woo Jin Lee; Byung Hoon Jeong; Geun Hee Cho; Jong Soo Lee; Gyung Su Byun; Changhyun Kim; Young Hyun Jun; Soo In Cho

A 1.4Gb/s DLL using 2nd order charge-pump scheme for low phase/duty error for high-speed DRAM application

Kyu hyoun Kim, Jung Bae Lee, Woo Jin Lee, Byung Hoon Jeong, Geun Hee Cho, Jong Soo Lee, Gyung Su Byun, Changhyun Kim, Young Hyun Jun, Soo In Cho

Samsung

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

A technique for reducing phase error of DLL/PLL due to non-ideal characteristics of the charge pump is proposed, it makes the output of the charge pump virtually grounded to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with the speed of 1.4Gb/s.

Original language	English
Pages (from-to)	166-167+504
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
State	Published - 2003
Externally published	Yes
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States Duration: 15 Feb 2003 → 19 Feb 2003

Cite this

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title = "A 1.4Gb/s DLL using 2nd order charge-pump scheme for low phase/duty error for high-speed DRAM application",

abstract = "A technique for reducing phase error of DLL/PLL due to non-ideal characteristics of the charge pump is proposed, it makes the output of the charge pump virtually grounded to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with the speed of 1.4Gb/s.",

author = "Kim, {Kyu hyoun} and Lee, {Jung Bae} and Lee, {Woo Jin} and Jeong, {Byung Hoon} and Cho, {Geun Hee} and Lee, {Jong Soo} and Byun, {Gyung Su} and Changhyun Kim and Jun, {Young Hyun} and Cho, {Soo In}",

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language = "English",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

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note = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement ; Conference date: 15-02-2003 Through 19-02-2003",

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AU - Kim, Kyu hyoun

AU - Lee, Jung Bae

AU - Lee, Woo Jin

AU - Jeong, Byung Hoon

AU - Cho, Geun Hee

AU - Lee, Jong Soo

AU - Byun, Gyung Su

AU - Kim, Changhyun

AU - Jun, Young Hyun

AU - Cho, Soo In

PY - 2003

Y1 - 2003

N2 - A technique for reducing phase error of DLL/PLL due to non-ideal characteristics of the charge pump is proposed, it makes the output of the charge pump virtually grounded to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with the speed of 1.4Gb/s.

AB - A technique for reducing phase error of DLL/PLL due to non-ideal characteristics of the charge pump is proposed, it makes the output of the charge pump virtually grounded to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with the speed of 1.4Gb/s.

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M3 - Conference article

AN - SCOPUS:2442716523

SN - 0193-6530

VL - 47

SP - 166-167+504

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement

Y2 - 15 February 2003 through 19 February 2003

ER -

A 1.4Gb/s DLL using 2nd order charge-pump scheme for low phase/duty error for high-speed DRAM application

Abstract

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