A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication

Majid Jalalifar; Gyung Su Byun

doi:10.1109/ASSCC.2016.7844144

A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication

Majid Jalalifar, Gyung Su Byun

Southern Methodist University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.

Original language	English
Title of host publication	2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	97-100
Number of pages	4
ISBN (Electronic)	9781509037001
DOIs	https://doi.org/10.1109/ASSCC.2016.7844144
State	Published - 6 Feb 2017
Externally published	Yes
Event	12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan Duration: 7 Nov 2016 → 9 Nov 2016

Publication series

Name	2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

Conference

Conference	12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016
Country/Territory	Japan
City	Toyama
Period	7/11/16 → 9/11/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

ASK
I/O
PAM
memory interface
on-chip channel

Access to Document

10.1109/ASSCC.2016.7844144

Cite this

Jalalifar, M., & Byun, G. S. (2017). A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings (pp. 97-100). Article 7844144 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2016.7844144

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abstract = "A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.",

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author = "Majid Jalalifar and Byun, {Gyung Su}",

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Jalalifar, M & Byun, GS 2017, A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication. in 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings., 7844144, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 97-100, 12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, 7/11/16. https://doi.org/10.1109/ASSCC.2016.7844144

A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication. / Jalalifar, Majid; Byun, Gyung Su.
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 97-100 7844144 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.

AB - A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.

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Jalalifar M, Byun GS. A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 97-100. 7844144. (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings). doi: 10.1109/ASSCC.2016.7844144

A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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Cite this